1. Field of the Invention
The present invention relates to an image display technique, and more particularly, to a proper dot clock reproducing technique when converting an analog video signal from a video signal output device such as a personal computer into a digital video signal and outputting the converted signal to a dot-matrix type image display apparatus, and to a technique that is applied to and is suitable for use in a multi-scan type liquid crystal display, a liquid crystal projector, and a plasma display, etc. to which a video signal according to an unspecified standard is inputted.
2. Description of the Related Art
In recent years, the most common image display apparatus of computers, etc. is a so-called multi-scan type image display apparatus capable of displaying an image signal having various frequencies (resolutions). In order to realize a multi-scan type image display apparatus using dot-matrix type image display apparatuses, typically, for example, liquid crystal displays and plasma displays, it is necessary to sample an analog image signal at a dot clock which coincides with a dot period of the image signal, to write the sampled signals into a memory, and to perform processes such as enlargement/reduction of the image so as to match the image with the resolution of an image display unit and other signal processing. Here, assuming that the image signal is sampled at a dot clock which is different from the frequency of an input image signal, not only is the number of horizontal valid pixels after sampling different from the number of horizontal valid pixels to be displayed on the image display unit, but also this causes phenomena such as moire fringes, etc., and thus the image quality deteriorates noticeably. However, since the image signal of the source which outputs the dot clock is small, the dot clock is reproduced by gradually multiplying the horizontal synchronizing signal in the image display apparatus. Therefore, it is necessary to provide a mechanism for positively reproducing the dot clock so that the input image signal is displayed without deterioration in the quality of the image.
A conventional image display apparatus adopts a method of determining the resolution of an image signal which is connected by using a horizontal synchronizing signal and a vertical synchronizing signal of an inputted image signal and determining a multiple for the gradual reduction of the dot clock from the determined result by referring to a table which is prepared in advance. However, the dot clock differs slightly from the prepared dot clocks depending on the connected source of the image signal and, in this case, the dot clock frequency is adjusted by manual adjustment while a user visually checks the displayed image.
Japanese Patent Laid-Open No. 10-078771 discloses an image display apparatus in which the manual adjustment is automated. FIG. 7 shows a construction of a dot clock generating device in the image display apparatus. Referring to FIG. 7, there is provided a sampling circuit 5 for sampling a video signal from a video output unit 2; a sampling clock generating circuit 7 for generating a sampling clock; a clock phase varying circuit 6; an image holding memory 4 for generating a clock; a phase control unit 8; a clock frequency control circuit 9 for controlling the frequency of the sampling clock which is generated by the sampling clock generating circuit 7; and a video output control unit 3. Those components form a dot clock generating device 1. An image display apparatus 13 has the dot clock generating device 1 and an image display circuit 14, and displays a video signal which is digitally converted by use of the sampling clock via the image display circuit 14.
In the construction, the video output unit 2 outputs a video signal including an image for generating the sampling clock which has a predetermined number of dots. Then, the clock frequency control circuit 9 counts the output period of the image for generating the sampling clock of the video signal by a clock having a proper period with a frequency higher than that of the dot clock of the video signal, thereby detecting the number of clock pulses for a one-dot period as [(the number of clock pulses for an n-dot period)/(the number of dots n)=(the number of clock pulses for one horizontal scanning period)]. Further, the number of clock pulses for one horizontal scanning period is counted, thereby obtaining the total number of dots for one horizontal scanning period as [(the number of clock pulses for one horizontal scanning period)/(the number of clock pulses for a one-dot period)=(the total number of dots for one horizontal scanning period)]. The obtained number is set in a dividing counter in the clock generating circuit 7, thereby automatically adjusting the frequency of the sampling clocks to the desired dot clock frequency.
However, according to the conventional image display apparatus in which the dot clock frequency is manually adjusted, a user must manually adjust the displayed image while viewing the displayed image when the dot clock frequency of the source of the image signal differs slightly from the dot clock frequency which is reproduced by the image display apparatus. Thus, this causes a problem in that not only does the operation become complicated but also it is difficult to accurately adjust the displayed image.
Also, according to the image display apparatus disclosed in Japanese Patent Laid-Open No. 10-078771, although the automatization of adjustment is realized, it is necessary to output an image signal for adjustment from the source of the image signal. Further, since a detection clock having a frequency higher than that of the dot clock of the input image signal is necessary so as to detect the total number of dots for one horizontal scanning period, the construction of the clock frequency control circuit must cope with an excessively high frequency and this results in the problem of increased costs.
In order to solve the above-mentioned problems, it is an object of the present invention to provide an image display apparatus capable of automatically adjusting a dot clock frequency without needing a specified image signal for adjustment and to provide an image display method. Further, it is an object of the present invention to provide an image display apparatus having a construction by which an operating speed of a circuit for adjusting a dot clock frequency is increased and costs are easily reduced, and to provide an image display method.
To accomplish the objects, according to a first aspect of the present invention, there is provided an image display apparatus for displaying an image to a dot-matrix type image display unit on the basis of an input image signal having an arbitrary standard, including an input dot clock reproducing circuit for reproducing an input dot clock on the basis of an input horizontal synchronizing signal of the input image signal, an A/D converting circuit for converting the input image signal into a digital signal in response to the input dot clock, an image display unit drive circuit for converting the digital signal into a display signal which is suitable to display by the image display unit and generating a drive timing signal for the display, a detecting circuit of the number of horizontal valid pixels for detecting the number of horizontal valid pixels of the display signal on the basis of the display signal and the drive timing signal, and an input dot clock control circuit for controlling a frequency of the input dot-clock so that the number of horizontal valid pixels is equal to a desired value.
Preferably, in the image display apparatus, the image display unit drive circuit comprises an image memory for temporarily storing the digital signal and generates a display horizontal synchronizing signal, a display vertical synchronizing signal, and a display dot-clock as the drive timing signals.
Preferably, in the image display apparatus, the image display unit drive circuit converts the digital signal into the display signal so that the numbers of horizontal and vertical pixels of the digital signal coincide with the numbers of horizontal and vertical pixels of the image display unit.
Preferably, in the image display apparatus, the input dot clock reproducing circuit includes a phase comparing circuit for comparing a phase of the input horizontal synchronizing signal with a phase of an internal feed-back signal and for outputting an error signal, a filter circuit for smoothing the output of the phase comparing circuit, a voltage control oscillating circuit for controlling an oscillating frequency by an electric potential which is smoothed by the filter circuit, and a 1/N-dividing circuit for dividing an oscillating signal of the voltage control oscillating circuit into N, thereby generating the internal feed-back signal.
Preferably, in the image display apparatus, the input dot clock control circuit obtains the desired number of horizontal valid pixels by controlling a dividing number N of the 1/N-dividing circuit.
Preferably, in the image display apparatus, the detecting circuit of the number of horizontal valid pixels detects a horizontal start position of the display signal as the number of displayed dot clocks until a valid display image signal is detected for each display horizontal scanning period and also detects a horizontal end position of the display signal as the number of displayed dot-clocks until the valid display image signal is not detected for each display horizontal scanning period.
Preferably, in the image display apparatus, the input dot clock control circuit has a CPU.
According to a second aspect of the present invention, there is provided an apparatus for detecting the number of horizontal valid pixels, including a dot clock counting circuit for starting counting of the number of dot clocks of an image signal to be inputted synchronously with a horizontal synchronizing signal of the image signal, a level detecting circuit for detecting whether or not there is a valid image signal in the image signal, a horizontal image start-position latching circuit for latching a minimum counted-number of the dot clocks until the valid image signal is detected for each horizontal scanning period of the image signal, and a horizontal image end-position latching circuit for latching a maximum counted-number of the dot clocks until the valid image signal is not detected for each horizontal sampling period of the image signal.
According to a third aspect of the present invention, there is provided an image display method for displaying an input image signal to an image display unit by use of a display dot-clock by sampling the input image signal by an input dot clock and by converting the signal into a display signal suitable to display to the image display unit, including the steps of detecting horizontal start and end positions of a valid signal in the converted display signal as the numbers of displayed dot-clocks until the valid display signal is detected and is not detected for each display horizontal scanning period, and controlling a frequency of the input dot-clock so that the number of horizontal valid pixels which is obtained on the basis of the detected result is equal to the desired value.
Preferably, the image display method further includes the steps of generating the input dot clock by an input dot clock reproducing circuit for generating a dot clock by converting an input horizontal synchronizing signal of the input image signal into a signal of a frequency corresponding to a dividing set value, and controlling a frequency of the input dot clock by adding a difference between the number of horizontal valid pixels which is obtained on the basis of the detected result and the desired number of horizontal valid pixels to the dividing set value.
Preferably, the image display method further includes the steps of generating the input dot clock by an input dot clock reproducing circuit for generating a dot clock by converting an input horizontal synchronizing signal of the input image signal into a signal of a frequency corresponding to a dividing set value, and controlling a frequency of the input dot-clock by multiplying the dividing set value by a ratio of the number of horizontal valid pixels which is obtained on the basis of the detected result to the desired number of horizontal valid pixels.
Preferably, according to the construction of the present invention, the number of horizontal valid pixels is detected on the basis of the display signal suitable to display to the image display unit, and the frequency of dot clocks is controlled so that the number of horizontal valid pixels is equal to a desired value. Therefore, the input dot clock is adjusted without needing the conventional manual adjustment and the image signal for adjustment. The number of horizontal valid pixels is detected by the displayed dot-clock which is used for display of the image display unit and, thus, it is unnecessary to use a circuit corresponding to a conventional remarkably higher frequency for the purpose of the detection of the number of horizontal valid pixels.